The present invention relates to a method of forming a pattern of a semiconductor device and, more particularly, to a method of forming a pattern of a semiconductor device, in which a gate pattern is formed in a cell region and a peri region at the same time.
A semiconductor device includes a plurality of gate lines (for example, memory cells and transistors) and metal lines. In order to increase the storage capacity of a semiconductor device and miniaturize the semiconductor device, the width of a plurality of patterns including gate lines and metal lines must be narrow.
In general, a patterning process of forming patterns includes forming a hard mask layer on a to-be-etched layer and forming photoresist patterns on the hard mask layer. Hard mask patterns are formed by performing an etch process along the photoresist patterns. The to-be-etched layer can be patterned by performing an etch process along the hard mask patterns.
To form the photoresist patterns, exposure and development processes are carried out. In particular, the width of a pattern is determined according to resolutions of a light source used during the exposure process. That is, there are limits in forming further micro patterns due to the limitation of resolutions.
After the patterns of the cell region are formed, if a Bottom Anti-Reflection Coating (BARC) layer is formed to form patterns of the peri region, a step can occur between the cell region and the peri region due to a difference between the patterns. If the photoresist layer is formed and the exposure process is performed in a state where the step exists, a notching phenomenon can be generated due to scattering of light in the step generating region. Thus, a polishing process for removing the step can be performed. This increases the steps of the fabrication process of the semiconductor device, which can result in increased fabrication costs and extended manufacturing time.